Pixel | CCD | Area Array | Line Array | Frame Transfer | Full Frame
Thinned Backside Illuminated | Interline Transfer | Dark Current
Long Term Integration | Slow Scan | Shot Noise
ENOB | Coorelated Double Sampling | Binning
1. Pixel - If an image scene is divided up in a checkerboard fashion, each resulting square (or rectangle) is known as a pixel, which stands for picture element . Each photosite of an area array CCD or a linear array CCD detects a specific area of an image. These photosites are also referred to as pixels.

2. CCD - Charge can be transported and stored in Silicon by forming regularly spaced electrodes over the Silicon and then manipulating the voltages of the electrodes to form potential wells, and blocking electrodes (to isolate the wells from one another). The electrodes are usually of polysilicon and insulated from the bulk silicon with silicon dioxide. Charge is stored at the potential well sites. By imaging through the semi-transparent electrode and insulator layers, charge is also created (and stored) that is a linear analog of the light intensity of the image at that pixel site. By clocking the electrodes in a multiphased manner, the wells can be caused to move in a specific direction. The charge will move with the wells. In a simple CCD structure, at least three phases are required. By using doped implants to manipulate the shape of the wells (virtual phase), two phase and even single phase operation is possible. The charge is read out by dumping the charge into an output diode, which acts as a storage capacitor, and then sensing the change in voltage across the diode with an MOS source follower amplifier.

3. Area Array - A CCD that has its photo sensors (pixels) arranged in columns and rows. Can image an entire scene at one time. Typical of camcorders and digital cameras. There are three varieties of area arrays:

  • Frame Transfer
  • Full Frame
  • Interline Transfer
4. Line Array - A CCD that has all of its photo sensors arranged in one line or row. To scan an image scene, the scene must be moved relative to an array. Typical of FAX machines and flat bed scanners.

5. Frame Transfer CCDs - Has two CCD area row/column arrays, one for imaging and one for image storage. The image area generates charge carriers (usually electrons) during the active portion of the video scan period. Each photosite or pixel in the image area consists of a semi-transparent electrode of polysilicon insulated from the bulk silicon by a thin insulating layer of silicon dioxide. This forms an MOS capacitor. Photons enter the silicon through the electrode and insulator where electron/hole pairs are produced by the photoelectric effect. The image charge is collected under the MOS electrode (in a potential well) that is biased to retain charge during the active video period of the video signal. The holes are conducted to ground through the silicon substrate. Photosites are electrically isolated from one another in their respective columns by electrodes that are biased to prevent charge from flowing out of the photosite. An implanted potential barrier is also provided between columns to isolate the photosites between columns. During the vertical timing interval, the electrode potentials are manipulated by multiphase clock signals to form a charge transport system per row (vertical analog shift registers). The image charge is thereby delivered and stored in a pixel array in the image storage area. Each pixel storage site also consists of an MOS capacitor. The image storage area is optically masked to prevent unwanted charge generation. During the next active image period the pixels are transferred a row at a time during the horizontal timing interval via the CCD shift register process, to a horizontal CCD analog shift register. The image charge is then shifted out of the horizontal register to an output amplifier to form one complete TV line. This is done until one field or frame is read out during the active image period. This method of transporting the image charge through the image area to the image storage area takes hundreds of microseconds while light is still generating image charge. Therefore, this process will generate considerable smear for a 30 frame per second "real time" application. Blocking the light during this shift process with a shutter operating at 60 times per second would not be practical. The semi-transparent polysilicon and silicon dioxide layers of the MOS capacitor photosite reduces the peak quantum efficiency to 25% to 30% and also further reduces the blue light sensitivity due to the optical interference filter effect of these layers. The interference effect also causes bumps across the spectral response of this type of CCD. Since the dielectric constant of silicon is wavelength dependent, partial reflection from the silicon will vary across the spectrum. Therefore, the quantum efficiency typically peaks in the red or near infrared portion of the spectrum.

6. Full Frame CCDs - Only requires the image area (which also acts as a column by column vertical analog shift register) and the horizontal analog shift register. During all charge transport, a shutter is used to prevent smear. Full Frame CCDs are therefore, necessarily slow and only have "non real time" operation. This CCD also suffers from the same interference effects as the Frame Transfer CCD. Since "real time" operation is not possible, lens focusing is more difficult. The full frame front side illuminated CCD suffers from the same spectral response problems as the Frame Transfer CCD. Peak quantum efficiency is typically 25% to 30%. These imagers are generally very expensive.

7. Thinned Backside Illuminated - Thinning and backside illumination is usually applied to Full Frame CCDs to improve peak quantum efficiency (as much as 90%) and to improve blue response. Photons enter the back side of the CCD where there are no electrodes to interfere with them. The thin silicon is required to allow the photon generated electrons to migrate to the MOS capacitor on the other side of the silicon before recombination with a hole can occur. By also applying an anti reflective coating the spectral response can be flattened to about 90% quantum efficiency across the spectrum. These imagers are extremely expensive.

8. Interline Transfer CCDs - Image frame storage is located between the columns of the photosites. The storage area is optically masked. The photosites are usually hole accumulation diodes that are fully exposed to the photons. Therefore, due to the absence of polysilicon and silicon dioxide layers, each site has a high quantum efficiency and good blue response. However, only half of the imaging area can produce charge carriers, which reduces the overall quantum efficiency. This was particularly true for older Interline CCDs. The newer Interline technology uses microlenses over the photosites to redirect the photons away from the masked storage area and onto the photosites, thus regaining the lost quantum efficiency. The image charge is transported from the photosites to the image storage area in tens of nanoseconds for virtually no smear. The image charge is then CCD transported to the to the horizontal register and out to the output amplifier to complete the process. Since most camcorders and industrial cameras use this type of CCD, good quality low cost CCD sensors are available. This is CTEC Photonic’s imager of choice because of:

  • Capable of both real time and long term integration operation
  • Low dark current (see 9.)
  • Good blue response
  • Good quantum efficiency
  • Extremely low smear
  • Mechanical shutter not required
  • Low cost cameras
9. Dark Current - Unwanted, thermally generated charge that is accumulated along with the image charge that is a function of temperature and time. Most of the dark current is generated because of surface states. Thermally active electrons can more effectively jump from the valence band to the surface state and then to the conduction band producing electron hole pairs. Dark current can be reduced in a full frame CCD by configuring it for the MPP mode of operation. MPP is implemented by using a special doping in the CCD structure and biasing the electrodes so that surface states are filled with holes and will thereby produce less dark current from surface states. MPP operation usually cannot support high speed real time operation and is usually used with Full Frame CCDs. Hole Accumulation Diode photosites used in Interline Transfer CCDs have this same affect, but without compromising speed of operation. There will be a measurable affect from dark current in a Frame Transfer CCD (non MPP) after about 0.3 seconds of integration. An interline transfer CCD using hole accumulation photosites can integrate for 3 to 5 seconds before a measurable amount of dark current can be detected. Dark current can be dramatically reduced by a factor of two for every 6° to 8°C reduction in temperature. Integration can be practically extended to 30 minutes and beyond at a temperature of -30°C in a Hole Accumulation Interline Transfer CCD (CTEC Photonic’s CCD of choice).

10. Long Term Integration - The longer charge is generated in the photosite due to photon interaction the more the sensitivity of the CCD camera is improved. Long term integration, however, is a "non real time" operation and is only practical for still frame imaging. During long term integration, Dark current is negated by cooling the CCD.

11. Dynamic Range - The dynamic range of a CCD is the ratio of the peak video signal to the RMS output amplifier noise (lens cap on), usually measured in dB units.

12. Slow Scan - The CCD output signal plus amplifier noise is detected in an integrating amplifier where the signal amplitude is a linear function of the integration time period and the noise amplitude is proportional to the square root of the integration time period. This integration time is the inverse of the clock rate. Therefore, slower clock rates will produce a larger dynamic range since the signal amplitude will grow faster than the noise amplitude. The slower the scan time the more improvement in dynamic range. Every time the integration time is doubled (halving the clock frequency) the SNR will increase by 3 dB.

13. Shot Noise - Caused by the granularity of individual photons or electrons. Shot noise is the square root of the number of electrons in a well. Therefore the SNR, due to shot noise only, is the ratio of the number of electrons to the square root of the number of electrons. Large well CCDs, typical of Full Frame CCDs, therefore produce superior SNR due to shot noise. Full Frame CCDs can have well sizes as large as 500,000 electrons per well resulting in an SNR of 57 dB due to shot noise. Most industrial grade CCDs have a well size of about 20,000 electrons resulting in an SNR due to shot noise of 43 dB.

14. ENOB - Effective Number of BITS. This is parameter that is used to select an Analog to Digital Converter (ADC) for a video camera. The standard of measure is based on equating the "SNR" of the camera to "SNR" of the ADC as limited by its quantization noise and number of bits. For the standard ENOB measurement, the signal magnitude is its RMS value. The signal is assumed to be a sine wave. i.e., SNR = 6N +2. The +2 term results from taking the ratio of the RMS signal and RMS. quantization noise. Therefore, N (or ENOB) = (SNR-2)/6. Beware, it has been the habit in the industry to equate the cameras "SNR" commonly expressed as the peak video to RMS noise to the "SNR" of ADC as expressed as the RMS value of a sine wave signal to RMS noise. This is a specmanship curve ball that compares apples to oranges. It is more important to be able to determine the accuracy of an individual pixel amplitude, Therefore, peak signal to RMS noise comparison between the camera and ADC is more relevant. With this in mind the ENOB is adjusted to, ENOB = (SNR-10.7)/6 where the SNR is the standard specification for the CCD camera. As an example, the ENOB for a 62 dB SNR using the standard ENOB measurement would be 10 bits, Whereas, if individual pixel identification is what your after, the ENOB should be only 8.5 bits.

15. Reset Noise - The output detection diode of a CCD must be purged of the previous pixel charge and set to a reference level prior to receiving the next pixel charge. Reset noise is introduced when the read-out diode is charged to its reference level and can be thought of as the inaccuracy of setting the diode reference level.

16. Correlated Double Sampling (CDS) - CDS is used to negate reset noise. A sample of the reset amplitude is saved prior to the arrival of the pixel charge. The reset amplitude is then subtracted from the pixel amplitude. Since the pixel amplitude is additive to the reset noise, the subtraction will eliminate the reset noise. CDS will also reduce 1/f noise.

17. Binning - By adding adjacent pixels, a super pixel can be created which will increase the sensitivity of the imager and increase the SNR due to shot noise. Increasing sensitivity will be beneficial in reducing integration time. Since fewer total pixels result, the user must decide on the tradeoff between increased sensitivity for lower resolution.